1. Field of the Invention
The present invention relates to an organic insulating film and a semiconductor device therewith and, more particularly, to a low-dielectric-constant organic insulating film and a manufacturing method thereof as well as a semiconductor device with a multi-layered interconnection structure wherein such a low-dielectric-constant organic insulating film is used for an interlayer insulating film and a manufacturing method thereof.
2. Description of the Related Art
In fabrication of the ICs (Integrated Circuits), accompanying advance in the speed of operation and the degree of integration in the device, further reduction in the device design rule has been in progress. The miniaturization of the interconnection size and the spacing of the interconnections made through such reduction in device size tend to increase the interconnection resistance and the capacitance between interconnections in inverse proportion thereto. Since these increases in interconnection resistance and capacitance between interconnections raise the RC time constant, the signal velocity is lowered, giving rise to a serious problem with respect to attaining higher speeds of operations in the device.
Accordingly, the reduction of the interconnection resistance and the capacitance between interconnections has become a matter of utmost importance to speed up operations in the device. With the object of reducing the interconnection resistance, the technique wherein copper having a lower electrical resistivity than aluminium hitherto widely used is employed as the interconnection material and the products manufactured therewith have become spreading.
Further, because the capacitance between interconnections increases in proportion to the area of interconnection and the dielectric constant of the insulating film separating interconnections and in inverse proportion to the distance between interconnections, for the sake of reducing the capacitance between interconnections without making any change in the device design, for instance, the use of an insulating film having a lower dielectric constant than the conventional oxide film (SiO2) and nitride film (SiN) has been, for example, being much investigated.
When Cu is used for the interconnection material, owing to the difficulty Cu has in microfabrication with dry etching, a damascene interconnection structure such as shown in FIG. 1 is, in general, widely employed.
In the method of forming a damascene interconnection, an etching stopper film SiN insulating film 003 having an excellent etching selectivity to an interconnection trench SiO2 interlayer insulating film 0002 that is to be formed subsequently, is first grown, on an underlying SiO2 interlayer insulating film 0001, to a thickness of 50 nm to 150 nm by the parallel plate type plasma CVD (Chemical Vapor Deposition) method with SiH4, NH3 and N2, and an interconnection trench SiO2 interlayer insulating film 0002 is then grown to a thickness of 400 nm to 1000 nm or so. Next, a trench pattern is formed by means of photolithography and dry etching, and thereafter the resist pattern is removed by means of O2 dry ashing and wet peeling-off. Using the sputtering technique and plating technique, the trench pattern is then filled up with Cu as well as a barrier metal such as Ta or TaN which is used to prevent the Cu diffusion and superfluous portions of the Cu and the barrier metal laid on the interconnection trench SiO2 interlayer insulating film 0002 are removed by the CMP (Chemical Mechanical Polishing) to form a Cu interconnection 0007.
In the case that an interlayer insulating film is formed after the damascene interconnection formation, because Cu is liable to react with SiO2 to diffuse out, a via plug SiO2 interlayer insulating film 0010 is normally grown after a SiN film 0012 is grown on the Cu as a diffusion-prevention insulating film (barrier insulating film) to a thickness of 50 nm to 100 nm or so by the parallel plate type plasma CVD method using SiH4, NH3 and N2.
Hereat, SiN not only prevents the Cu diffusion but also acts as am etching stopper layer for the SiO2 film so that the Cu surface may be prevented from being exposed to the atmosphere of SiO2 etching at the time of the trench etching for the Cu and the atmosphere of O2 resist ashing at the time of forming a via hole above a damascene interconnection of Cu. SiN is, in effect, required to work for prevention of the diffusion and, at the same time, function as an etching stopper layer.
In recent years, for the purpose of reducing the parasitic capacitance between interconnections further, there have been widely investigated the use of an organic insulating film of SiOF, SiOC or such, which has a lower dielectric constant than that of a conventional SiO2 film of 4.1, together with the use of an organic insulating film of SiC or SiCN with a dielectric constant of 4.5 to 5 or so, formed by the parallel plate type plasma CVD method using, as a source, 4MS (tetramethylsilane) or 3MS (triethylsilane) which has a lower dielectric constant than that of SiN of 7.
FIGS. 15(a) to 16(c) illustrate a conventional method in which SiC films or SiCN films grown conventionally using 3MS as a source gas are employed.
After forming a first Cu interconnection 805, a second SiCN film 806 is grown, using the afore-mentioned gas. Next, a second SiOC film 807 and a third SiCN film 808 are formed, in the same way, using the afore-mentioned gas and, thereon, a third SiOC film 809 and a second SiO2 film 810 are grown.
As shown in FIG. 15(a), using, as a mask, a photoresist where a resist pattern for via hole is formed, etching is applied onto the second SiO2 film 810, the third SiOC film 809, the third SiCN film 808 and the second SiOC film 807 to be terminated above the second SiCN film 806.
However, there are occasions in which the etching selection ratio between SiOC and SiCN is small so that the etching proceeds to the interconnection lying in the lower layer as shown in FIG. 15(b). In that case, when ashing by O2 gas is thereafter carried out to peel off the photoresist, an oxide layer 831 of Cu is formed in a region where the Cu interconnection has been subjected to the etching. The same also happens when a film of either of SiOC and SiC is utilized.
Next, as shown in FIG. 15(c), after applying a coating of an anti-reflection coating film thereto, a second resist pattern for trench interconnection 819 is formed through a photoresist 818.
As shown in FIG. 15(d), using the photoresist 818 as a mask, etching is applied to the second SiO2 film 810 and the third SiC film 808. After that, the photoresist 818 is peeled off by oxygen ashing, which may result in further oxidation of the afore-mentioned oxide layer 831 of Cu, and thereafter the organic peeling-off is carried out.
With the entire surface etch-back, the second SiCN film 806 is then etched away, as shown in FIG. 16(a). Next, as shown in FIG. 16(b), after a second Ti/TiN film 820 is formed, a second Cu film 821 is formed. Subsequently, the metal other than the trench interconnection is removed to form a second Cu interconnection 832. Thereon, a fourth SiCN film 822 is formed, as shown in FIG. 16(c).
The SiC film, the SiCN film and the SiOC film formed by the parallel plate type plasma CVD method using, as a source material, 4MS (tetramethylsilane) or 3MS (trimethylsilane) are currently under wide investigation. The dielectric constants for SiC and SiCN are 4.5 to 5 or so, and the dielectric constant for SiOC is 2.8 to 3.0 or so.
With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.
Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.